29 lines
1.2 KiB
Markdown
29 lines
1.2 KiB
Markdown
---
|
|
title: Notes - 2. PHY Layer
|
|
date: 1970-01-01T00:00:00.000Z
|
|
slug: notes-phy
|
|
---
|
|
|
|
### 2. PHY?
|
|
|
|
What is PHY? Physical Layer from OSI Layers.
|
|
Usually indicates the chip/part where parses incoming signal (via RF or cable) and then send it to next layer in standardized way. ADC. Analog singal to digital data.
|
|
Raw Analog <--> Amplifing, Filtering, Equalizing <--> Decoding, Encoding, Error checking (CRC), Clock Data Recovery.. <--> Data Link
|
|
|
|
PHY Designs?
|
|
Line Driver / Amplifier for better analog resolution
|
|
PLL (Phase-Locked Loops) for CDR and matching clocks from incoming clock/data signal.
|
|
DSP (Digital Singal Processor) for processing raw data to known format data.
|
|
|
|
Eth PHY.
|
|
MAC. (Media Access Control) <-> PHY via MII GMII (Media Independant Interface)
|
|
PHY just transform Ethernet Cable signal into data packet.
|
|
From MAC, actual content of data is interpreted, MAC distinguishes each devices, de/encapsulates.
|
|
|
|
Line Driver?
|
|
Part of transmission line signal. Make sure right signal arrived well. Matching impedence.. etc... (how? and what more?)
|
|
|
|
DSP Design?
|
|
For example in Eth PHY what is processed in DSP? Deserialization? ( Parsing differential signals? => line driver maybe )
|
|
|